Conventional EEPROMs typically employ three to four transistors, which include a tunnel diode device coupled to the floating gate of the sense transistor to charge the latter and a select or row transistor to activate the cell. The use of three or four transistors to realize a cell substantially limits the size reduction possible for EEPROM arrays. Furthermore, typical EEPROM cells require the application of voltages in excess of 15 volts. This therefore requires special processing to reduce leakage and a larger layout to avoid unwanted field transistor turn-on, i.e., the use of high voltage transistors typically have longer channel lengths, and therefore, significantly larger sizes. This is especially the case with respect to the row transistor, since high voltage is applied to the source during the ERASE mode. The peripheral driving circuitry also requires higher voltage transistors to handle these high voltage driving signals.
One technique for reducing the voltage is to utilize lower voltages during the programming and the ERASE modes with use of an asymmetric transistor. This is disclosed in U.S. Pat. No. 4,939,558, issued Jul. 30, 1990, which patent is incorporated herein by reference. U.S. Pat. No. 4,939,558, discloses an asymmetric memory cell that utilizes Fowler-Nordheim tunneling techniques, whereby a reach-through region is provided on only one side of the floating gate, such that the tunneling of electrons takes place only on the reach-through side of the gate and, as such, creates an asymmetry in the transistor for the purposes of both programming and erasure.